1. Field of the Invention
The invention relates to a method for manufacturing a multi-gate transistor device.
2. Description of the Prior Art
Conventional planar metal-oxide-semiconductor (MOS) transistor has difficulty when scaling to 65 nm and below. Therefore the non-planar transistor technology such as Fin Field effect transistor (FinFET) technology that allows smaller size and higher performance is developed to replace the planar MOS transistor.
Please refer to FIG. 1, which is a schematic drawing of a conventional FinFET device. As shown in FIG. 1, the conventional FinFET device 100 is formed by: first a single crystalline silicon layer of a silicon-on-insulator (SOI) substrate 102 is patterned to form a fin film (not shown) in the SOI substrate 102 by proper etching process. Then, an insulating layer 104 covering the fin film is formed and followed by forming a gate 106 covering the insulating layer 104 and the fin film. Next, ion implantation and anneal treatment are performed to form a source/drain 108 in the fin film not covered by the gate 106. Since the manufacturing processes of the FinFET device 100 are easily integrated into the traditional logic device processes, it provides superior compatibility. Furthermore, when the FinFET device 100 is formed on the SOI substrate 102, traditional shallow trench isolation (STI) is no longer required. More important, since the FinFET device increases the overlapping area between the gate and the substrate, the channel region is more effectively controlled. This therefore reduces drain-induced barrier lowering (DIBL) effect and short channel effect. In addition, the channel region is longer under the same gate length, and thus the current between the source and the drain is increased.
However, because the source/drain 108 is a slim structure, it always suffers larger resistance and renders adverse impact to the electrical performance of the FinFET device 100. Furthermore, it is found since the source/drain 108 is a slim structure, alignment between the source/drain 108 and the contact plug in the following contact process becomes complicated and difficult. And thus process window of the contact process is adversely influenced.